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So I am trying to learn verilog, I have a conter,
reg counter;
And am expecting it to reach 15 at some point, but it never does it goes between 1 and 0. It works when I declare counter as a integer everything works. Well reg by default is just 1 bit adding 1+0 = 1 and 1+1=0, declaring as reg [31:0] counter fixed the problem.
reg counter;
And am expecting it to reach 15 at some point, but it never does it goes between 1 and 0. It works when I declare counter as a integer everything works. Well reg by default is just 1 bit adding 1+0 = 1 and 1+1=0, declaring as reg [31:0] counter fixed the problem.
